? die datasheet ga01pns100-cau feb 2015 http://www.genesicsemi.c om/high-temperature-sic/high- temperature-sic-bare-die/ page 1 of 5 ? silicon carbide pin diode chip features die size = 2.4 mm x 2.4 mm ? 10 kv blocking ? 210 c operating temperature ? fast turn off characteristics ? soft reverse recover y characteristics ? ultra-fast high temperature switching advantages applications ? industrys lowest conduction losses ? reduced stacking ? reduced system complexity/increased reliability ? ? ignition/trigger circuits ? oil/downhole ? lighting ? defense maximum ratings at t j = 210 c, unless othe rwise specified parameter symbol conditions values unit repetitive peak reverse voltage v rrm 10 kv continuous forward current i f t c 150 c 2 a rms forward current i f ( rms ) t c 150 c 1 a operating and storage temperature t j , t stg -55 to 210 c electrical characteristics at t j = 210 c, unless otherwise specified parameter symbol conditions values unit min. typ. max. diode forward voltage v f i f = 2 a, t j = 25 c 4.4 4.8 v i f = 2 a, t j = 210 c 4.1 4.5 reverse current i r v r = 10 kv, t j = 25 c 0.1 3 a v r = 10 kv, t j = 210 c 50 total reverse recovery charge q rr i f i f,max di f /dt = 70 a/s t j = 210 c v r = 1000 v i f = 1.5 a 558 nc switching time t s v r = 1000 v i f = 1.5 a < 236 ns total capacitance c v r = 1 v, f = 1 mhz, t j = 25 c 20 pf v r = 400 v, f = 1 mhz, t j = 25 c 5 v r = 1000 v, f = 1 mhz, t j = 25 c 4 total capacitive charge q c v r = 1000 v, f = 1 mhz, t j = 25 c 5 nc v rrm = 10000 v i f @ 25 o c = 2 a q c = 5 nc ?
? die datasheet ga01pns100-cau feb 2015 http://www.genesicsemi.c om/high-temperature-sic/high- temperature-sic-bare-die/ page 2 of 5 ? figures: figure 1: typical forward characteristics figure 2: typical reverse characteristics figure 3: typical junction capacitance vs reverse voltage characteristics figure 4: typical turn off characteristics at i k = 0.5 a and v r = 1000 v figure 5: typical turn off characteristics at t j = 210 c and v r = 1000 v figure 6: reverse recovery charge vs cathode current
? die datasheet ga01pns100-cau feb 2015 http://www.genesicsemi.c om/high-temperature-sic/high- temperature-sic-bare-die/ page 3 of 5 ? figure 7: reverse recovery time vs cathode current
? die datasheet ga01pns100-cau feb 2015 http://www.genesicsemi.c om/high-temperature-sic/high- temperature-sic-bare-die/ page 4 of 5 ? mechanical parameters die dimensions 2.4 x 2.4 mm 2 a node pad size 0.98 mm a rea total / active 5.76/0.75 mm 2 die thickness 450 m wafer size 76.2 mm flat position 0 deg die frontside passivation polyimide a node pad metallization 400 nm ni + 200 nm au backside cathode metallization 400 nm ni + 200 nm au die attach electrically conduc tive glue or solder wire bond au 26 m reject ink dot size 0.3 mm recommended storage environment store in original cont ainer, in dry nitrogen, < 6 months at an ambient temperature of 23 c chip dimensions: die a [mm] 2.4 b [mm] 2.4 metal c [mm] 0.98
? die datasheet ga01pns100-cau feb 2015 http://www.genesicsemi.c om/high-temperature-sic/high- temperature-sic-bare-die/ page 5 of 5 ? revision history date revision comments supersedes 2015/02/24 1 inserted mechanical parameters 2012/08/15 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. res erves right to make changes to t he product specifications and dat a in this document without not ice. genesic disclaims all and any warranty and liability arising ou t of use or application of any product. no license, express or implied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons syst ems, nor in applications where their failure may result in deat h, personal injury and/or property damage.
? die datasheet ga01pns100-cau sep 2013 http://www.genesicsemi. com/high-temperature-sic/high- temperature-sic-bare-die/ page 1 of 1 ? spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website (http://www.genesicsemi.com/images/hit_sic/baredie/pin/ga01pns1 00-cau_spice.pdf) into ltspice (version 4) software for simulation of the ga01pns100-cau devic e. * model of genesic semiconductor inc. * * $revision: 1.0 $ * $date: 05-sep-2013 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * ? http://www.genesicsemi.com/index.php/hit-sic/baredie * * copyright (c) 2013 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * * start of ga01pns100-cau spice model * ? .model ga01pns100 d + is 1.00e-25 + rs 0.49 + n 2.1612 + ikf 0.043903 + eg 3.23 + xti 10 + trs1 -0.00155 + cjo 2.28e-11 + vj 2.304 + m 0.376 + fc 0.5 + bv 11000 + ibv 1.00e-03 + vpk 10000 + iave 1 + type sic_pin + mfg genesic_semi * * end of ga01pns100-cau spice model
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